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针对工业上对计数器的需求以及计数器扩展存在的问题，充分应用FPGA的并行处理功能，提出了一种模块内部串行处理，各模块间并行执行的计数器IP核的设计方法，设计了系统的电路结构，指令格式，并行处理模块电路和串行处理流程程序，研制的计数器IP核具有多达14个16位或6个32位的计数器，能够自动重新装载计数参数，选择计数输入脉冲滤波参数等功能。经仿真验证了研制的计数器IP核功能的正确性。
In order to solve the problem of counter counter expansion in industry and make full use of parallel processing function of FPGA, a design method of counter IP core in serial processing and parallel execution of each module is proposed. The design of system circuit Structure, instruction format, parallel processing module circuit and serial processing flow program developed counter IP core with up to 14 16-bit or 6 32-bit counter, can automatically reload the count parameters, select the count input pulse filter parameters Features. The simulation verifies the correctness of the developed counter IP core function.