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介绍在ERES-寄存器级描述语言的基础上开发的ERES-ET计算机设计的模拟验证环境.该系统已用于RISC机与新型计算机的设计验证,并用于计算机辅助教学.
This paper introduces the simulation and verification environment of ERES-ET computer design based on ERES-register level description language.The system has been used in the design validation of RISC and new computer and used in computer-assisted instruction.