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针对在传统串行结构上执行图象匹配算法时影响执行速度提高的原因，通过分析图象匹配算法的内部流水性、并行性，提出了一种加速执行图象匹配算法的硬件并行结构。通过引入流水线数据延迟及多个并行处理单元，该结构使得重复读取存贮器的操作次数大大减少，从而加速完成图象匹配操作。文中给出了该结构的实现框图，并计算了采用该结构执行图象匹配算法所需时间。计算表明，对大小为６４×６４的搜索象、３２×３２的模板象，该结构可在不到９ｍｓ时间内完成全部图象匹配操作。利用相同原理，该结构也可对更大搜索、模板象的匹配过程实现实时或加速。
Aiming at the reasons that affect the execution speed when executing the image matching algorithm on the traditional serial structure, a hardware parallel structure for accelerating the execution of the image matching algorithm is proposed by analyzing the internal flow and parallelism of the image matching algorithm. By introducing pipelined data delays and multiple parallel processing units, this architecture greatly reduces the number of repetitive reads and therefore accelerates the image matching operation. The block diagram of this structure is given in this paper, and the time needed to implement the image matching algorithm using this structure is calculated. The calculation shows that for a search image of size 64 × 64 and a template image of 32 × 32, the entire image matching operation can be completed in less than 9 ms. Using the same principle, the structure can also achieve real-time or accelerated matching of larger search, template images.