论文部分内容阅读
This paper presents a direct digital frequency synthesizer(DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 0.98 mm2 and total power consumption of 300 m W at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.
This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 0.98 mm2 and total power consumption of 300 m W at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.