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提出了一种基于混合型数字脉宽调制器(HDPWM)的带延迟线二分法校准机制的新电路结构,能有效地提高DPWM的线性度。详细介绍了混合型DPWM的工作原理,阐述了基于二分法机制的自校准电路的整体结构。分析了该结构的后仿真结果,并与带延迟锁相环(DLL)结构的DPWM的后仿真结果相比较。在32 MHz的时钟下,该电路成功实现了开关频率为2 MHz的数字DC-DC变换器中的9-bit DPWM。该电路基于0.13μm 1.2V CMOS工艺实现,最大差分非线性(DNL)仅为0.136 LSB,积分非线性(INL)为0.15 LSB。
A new circuit structure based on hybrid digital pulse width modulator (HDPWM) with a two-part calibration method with delay line is proposed, which can effectively improve the linearity of DPWM. The working principle of hybrid DPWM is introduced in detail, and the whole structure of self-calibration circuit based on dichotomy is expounded. The post-simulation results of this structure are analyzed and compared with the post-simulation results of DPWM with a delay-locked-loop (DLL) structure. The circuit successfully implemented a 9-bit DPWM in a digital DC-DC converter with a 2 MHz switching frequency at a 32 MHz clock. The circuit is based on a 0.13μm 1.2V CMOS process with a maximum differential nonlinearity (DNL) of only 0.136 LSB and an integrated nonlinearity (INL) of 0.15 LSB.