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随着数字集成电路(IC)的设计变得更加复杂,验证其功能的工作也越来越复杂了。在能被设计的门电路数量和能在合理时间内被验证的门电路数量之间一直存在差距,而这些年来,EDA厂商们在缩小这种差距方面几乎无所作为。
As the design of digital integrated circuits (ICs) becomes more complex, the task of verifying their capabilities has become more complicated. There is always a gap between the number of gates that can be designed and the number of gates that can be verified in a reasonable amount of time, and EDA vendors have done little to narrow the gap over the years.