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采用VHDL语言输入，综合工具综合的自顶向下的设计方法是当前电子设计发展的趋势。但VHDL语言本身是基于仿真，而不是专为综合而设计的，许多VHDL语言结构在综合时将会引起一系列的问题。本文详细地分析了VHDL语言的可综合性问题。
The use of VHDL language input, integrated tools for top-down synthesis of integrated design method is the current trend of electronic design. But the VHDL language itself is based on simulation, rather than designed for synthesis, many VHDL language structure will cause a series of problems. This article analyzes in detail the synthesizable issue of VHDL language.