论文部分内容阅读
基于SMIC 0.18μm CMOS工艺,设计了一种10位自补偿逐次逼近(SAR)A/D转换器芯片。采用5+5分段式结构,将电容阵列分成高5位和低5位;采用额外添加补偿电容的方法,对电容阵列进行补偿,以提高电容之间的匹配。采用线性开关,以提高采样速率,降低功耗。版图布局中,使用了一种匹配性能较好的电容阵列,以提高整体芯片的对称性,降低寄生参数的影响。在输入信号频率为0.956 2MHz,时钟频率为125MHz的条件下进行后仿真,该A/D转换器的信号噪声失真比(SNDR)为61.230 8dB,无杂散动态范围(SFDR)达到75.220 4dB,有效位数(ENOB)达到9.87位。
Based on the SMIC 0.18μm CMOS process, a 10-bit self-compensated successive approximation (SAR) A / D converter chip is designed. A 5 + 5 segmented structure is adopted to divide the capacitor array into high 5 bits and low 5 bits. The capacitor array is compensated with an additional compensation capacitor to improve the matching between the capacitors. Linear switches are used to increase the sampling rate and reduce power consumption. Layout layout, the use of a better matching capacitor array to improve the overall chip symmetry and reduce the impact of parasitic parameters. The simulation results show that the signal-to-noise ratio (SNDR) of the A / D converter is 61.230 8dB and the spurious-free dynamic range (SFDR) is 75.220 4dB after the input signal frequency is 0.956 2MHz and the clock frequency is 125MHz. The number of bits (ENOB) reaches 9.87 bits.