采用TSMC0.18μm CMOS工艺实现了一个20Gbit/s1∶2分接器,分接器由主-从-从、主-从D触发器和数据输出缓冲组成.D触发器单元采用动态负载结构,其偏置晶体管采用单时钟输入的共栅结构.动态负载结构的触发器工作速度更快因为它减小了输出点的冲放电时间,而且由于工作时电流处于开关模式,其功耗更低.另外,触发器中采用交叉耦合的正反馈三极管对,加快了整个电路的速度.通过在片晶圆测试,该芯片在输入20Gbit/s、长度为223-1的伪随机码时工作良好.功耗仅为108mW,芯片面积为475μm×578μm. A 20Gbit / s 1: 2 tap is implemented by using TSMC 0.18μm CMOS technology, and the tap is composed of master-slave-slave, master-slave D flip-flop and data output buffer.The D flip-flop unit adopts dynamic load structure Bias transistors use a single-clock input common-gate structure. The dynamic load structure flip-flop operates faster because it reduces the punch-out time at the output point and consumes less power because of the switch-mode current during operation. , The flip-flop uses a cross-coupled positive feedback transistor pair, speeding up the entire circuit.Through the wafer test, the chip in the input 20Gbit / s, the length of 223-1 pseudo-random code works well. Only 108mW, the chip area is 475μm × 578μm.