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加利福尼亚州的富士通微电子公司报导他们已研制了能贮存1M 位数据的 DRAM,预计在1986年底能大量生产。该器件采用 NMOS 技术,最小线宽为1.4μm。采用了三维叠式电容器单元的结构,在26.5μm~2的单元面积内可提供55pF 的数据存贮容量。该 DRAM 存取时间为90ns(t/rac)和45ns(t/cac),功耗为350mW(工作)和15mW(待机),用单一5V 电源,芯片面积为12.32mm×4.44mm,单元面积为8.4μm×3.15μm。另报导,东芝在美国的分公司研制了1M 位 CMOS DRAM,存取时间为100ns,最大工作电流40mA(待机时为1mA),使用1.2μm 设计规则。
Fujitsu Microelectronics of California reported that they have developed a DRAM that can store 1M data and is expected to be mass-produced by the end of 1986. The device uses NMOS technology, the minimum line width of 1.4μm. The structure of the three-dimensional stacked capacitor cell is adopted, and a data storage capacity of 55 pF is provided in a cell area of 26.5 μm to 2. The DRAM accesses 90ns (t / rac) and 45ns (t / cac), 350mW (active) and 15mW (standby), with a single 5V supply, a chip area of 12.32mm x 4.44mm and a cell area of 8.4 μm × 3.15 μm. Another report, Toshiba in the United States has developed a branch of 1M CMOS DRAM, access time of 100ns, the maximum operating current of 40mA (1mA standby), the use of 1.2μm design rules.