论文部分内容阅读
为提高射频功放的线性和效率,提出了一种基于多比特带通△∑调制器(BPDSM)的射频数字功放结构并给出了BPDSM的设计方法。针对调制器CRFB实现结构中关键路径过长的问题,利用重定时、流水线和超前计算等技术对实现结构进行了改进,将BPDSM的实现速率提高至200 MHz。提出了多电平开关功放的电路结构,将多个具有独立电源的开关功放单元进行串联,实现了对BPDSM输出多比特脉冲信号的高效开关放大。最后,利用FPGA器件及分立元件实现了频率为30 MHz的数字功放,输出功率为10 W时效率达到60%。
In order to improve the linearity and efficiency of RF power amplifiers, a RF digital power amplifier architecture based on multi-bit band-pass delta sigma modulator (BPDSM) is proposed and the design method of BPDSM is given. Aiming at the problem of too much critical path in the modulator CRFB structure, the implementation structure is improved by using such techniques as retiming, pipelining and advanced computation, and the realization rate of BPDSM is raised to 200 MHz. The circuit structure of multi-level switching power amplifier is proposed, and a plurality of switching power amplifier units with independent power supplies are connected in series to achieve high-efficiency switching amplification of BPDSM output multi-bit pulse signals. Finally, the use of FPGA devices and discrete components to achieve a frequency of 30 MHz digital amplifier, the output power of 10 W efficiency of 60%.