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对10只808nm大功率激光二极管进行室温恒电流老化,4只器件出现随机失效。采用高倍显微镜、激光扫描共焦显微镜和扫描电子显微镜(SEM)等方法对失效器件的近场光斑、腔面形貌、p面形貌及谐振腔截面形貌等进行了观察分析。在失效样品的芯片腔面或内部发现了不同程度的晶体熔毁缺陷,并且发现激光二极管功率衰减幅度与熔毁缺陷的位置及严重程度有关,确认芯片有源区的晶体熔毁缺陷是导致808nm大功率激光二极管随机失效的主要模式。分析认为材料生长过程的晶体缺陷、芯片制作过程中引入的损伤粘污缺陷以及封装过程中引入的损伤缺陷可能是晶体熔毁缺陷产生的最初原因。某些缺陷在加电老化过程中不断生长变大,造成谐振腔内损耗增加,激光二极管输出功率降低;同时谐振腔内光损耗导致芯片局部温度升高,加速缺陷生长变大。这种反馈过程使缺陷生长加速,在相对较短的时间内形成大面积晶体熔毁,导致激光二极管灾变失效。提高大功率激光二极管可靠性的根本方法是降低芯片制造过程引入的缺陷,同时严格控制封装散热以及封装应力。
Ten 808nm high-power laser diodes were galvanostatically aged at room temperature, and four devices failed randomly. The near-field flaw, cavity topography, p-topography and cavity cross-sectional morphology of the failed device were observed and analyzed by high magnification microscope, laser scanning confocal microscope and scanning electron microscope (SEM) Different levels of crystal meltdown defects were found in the cavity surface or inside the failed samples, and it was found that the power attenuation range of the laser diodes was related to the location and severity of the meltdown defects. It was confirmed that the crystal meltdown defects in the active region of the chip resulted in 808 nm High-power laser diode random failure of the main mode. It is considered that the crystal defects in the material growth process, the damage and adhesion defects introduced in the chip manufacturing process and the damage defects introduced in the packaging process may be the initial reasons for crystal melting defects. Some defects continue to grow and increase during the aging process, causing the loss in the resonator to increase and the output power of the laser diode to decrease. Meanwhile, the optical loss in the resonator causes the local temperature of the chip to increase, accelerating the growth of defects. This feedback process accelerates the growth of the defect, forming a large area of crystal meltdown in a relatively short period of time, causing the laser diode to fail catastrophically. The fundamental method to improve the reliability of high-power laser diodes is to reduce the defects introduced in the chip manufacturing process while strictly controlling the package heat dissipation and package stress.