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Look Up Tables(LUTs)are the key components of Field-Programmable Gate Arrays(FPGAs).Many LUT architectures have been studied;nevertheless,it is difficult to quantificationally evaluate an LUT based architecture.Traditionally,dedicated efforts on specific modifications to the technology mapping tools are required for LUT architecture evaluation.A more feasible evaluation method for logic functionality is strongly required for the design of LUT architecture.In this paper,a mathematical method for logic functionality calculation is proposed and conventional and fracturable LUT architectures are analyzed.Furthermore,a cascaded fracturable LUT architecture is presented,which achieves twice logic functionality compared with the conventional LUTs and fracturable LUTs.
Look Up Tables (LUTs) are the key components of Field-Programmable Gate Arrays (FPGAs). Many LUT architectures have been studied; nevertheless, it is difficult to quantificationally evaluate an LUT based architecture. Traveled, dedicated efforts on specific modifications to the technology mapping tools are required for LUT architecture evaluation. A more feasible evaluation method for logic functionality is strongly required for the design of LUT architecture. This paper, a mathematical method for logic functionality calculation is proposed and conventional and fracturable LUT architectures are analyzed. Stillrthermore , a cascaded fracturable LUT architecture is presented, which achieves twice logic functionality compared with the conventional LUTs and fracturable LUTs.