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An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For power optimization,the voltage supply of the digital part is lowered,and the offset voltage of the latch is self-calibrated.Targeted for better linearity and lower noise,an improved digital-to-analog converter capacitor array layout strategy is presented,and a low kick-back noise latch is proposed.The chip was fabricated by using 0.18μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only,resulting in a figure of merit of 220 fJ/conversion-step.The ADC core occupies an active area of only 674×639μm~2.
An ultra-low power 12 bits 2 kS / s successive approximation register analog-to-digital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self- calibrated. Targeted for better linearity and lower noise, an improved digital-to-analog converter capacitor array layout strategy is presented, and a low kick-back noise latch is proposed. The chip was fabricated by using 0.18 μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only, resulting in a figure of merit of 220 fJ / conversion-step. The ADC core occupies an active area of only 674 × 639 μm ~ 2.