中国科学院半导体研究所王守觉院士、石寅研究员领导的半导体神经网络及模糊逻辑高速电路实验室在新型高速直接数字频率合成(DDS)芯片研制中取得重大进展:他们采用0.35μm常规CMOS工艺研制出合成时钟频率达2 GHz的新一代ROM- LESS DDS高速芯片。目前国际上报道的同类芯片合成时钟频率为1.2 GHz,半导体所研制的芯片速度指标处于国际领先位置。此外,与本项高速DDS Chinese Academy of Sciences Institute of semiconductor researcher Wang Shou-ji, Shi Yin researchers led by semiconductor neural network and high-speed fuzzy logic circuit laboratory in the new high-speed direct digital synthesis (DDS) chip made significant progress: they use 0.35μm conventional CMOS technology developed synthesis A new generation of ROM-LESS DDS chips with clock frequencies up to 2 GHz. At present, the synthesized clock frequency of the same chip reported in the world is 1.2 GHz, and the chip speed index developed by the semiconductor is in the leading position in the world. In addition, with this high speed DDS