本文通过对具有引起低阻抗的内部桥接缺陷的单相动态模块进行单相时钟动态CMOS集成电路的电流测试分析,得出结果表明,电流测试是对通常逻辑测试方法的有效补充。由于内部桥接缺陷在电路中产生不高不低的电平,使得基于电平比较的逻辑测试方法难以奏效。本文还给出可进行电流测试的单相内部桥接的理论范围。 In this paper, single-phase dynamic model of a single-phase clock dynamic CMOS integrated circuit with internal bridging defects that cause low impedance is analyzed. The results show that the current test is an effective complement to the usual logic test methods. Due to the internal bridging defects in the circuit to produce high and low level, making the level comparison based logic test method is difficult to work. This article also gives the theoretical range of single-phase internal bridging that can be used for current testing.