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基于65nm CMOS工艺,设计了一种10位80 Ms/s的逐次逼近A/D转换器。该A/D转换器采用1.2V电源供电以及差分输入、拆分单调的DAC网络结构。采用拆分单调的电容阵列DAC,可以有效降低A/D转换所消耗的能量,缩短DAC的建立时间,降低控制逻辑的复杂度,提高转换速度;避免了由于比较器共模电平下降过多引起的比较器失调,从而降低了比较器的设计难度,改善了ADC的线性度。动态比较器降低了A/D转换的功耗。使用Spectre进行仿真验证,结果表明,当采样频率为80MHz,输入信号频率为40MHz时,该A/D转换器的SFDR为72dBc。
Based on 65nm CMOS technology, a 10-bit 80 Ms / s successive approximation A / D converter is designed. The A / D converter with 1.2V power supply and differential input, split monotone DAC network structure. The monolithic capacitor array DAC can effectively reduce the energy consumed by A / D conversion, shorten the setup time of DAC, reduce the complexity of control logic and improve the conversion speed. It avoids the problem that the common mode level drops too much Caused by the comparator imbalance, thereby reducing the design of the comparator more difficult to improve the linearity of the ADC. Dynamic comparators reduce the power consumption of A / D conversion. Using Specter simulation results, the results show that when the sampling frequency is 80MHz, the input signal frequency of 40MHz, the A / D converter SFDR is 72dBc.