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1 前言对于 MOS 晶体管的栅氧化膜来说,按照高集成化、高性能化的比例要求,在采用0.35μm 工艺技术的64MDRAM 中,要求薄膜减薄到10nm,而在0.25μm的256MDRAM 中则要减薄到8nm。对于高性能 CMOS 逻辑电路来说,在薄膜化方面的要求比DRAM 还要早一个时代,对于0.25μm 工艺来说,则要求使用6nm 这样极薄的氧化膜。为了降低热载流子对可靠性的影响,电源电压将从5V 调得更低一些,各类栅氧化膜大体上都会附加一定的电场。但是,对于高集成化来说,由于芯片面积的增大,也就是说,伴随栅面积的增大而如果
1 Introduction MOS gate oxide film MOS, in accordance with the requirements of high integration, high performance ratio, using 0.35M technology 64MDRAM, the film is required to be thinned to 10nm, and 0.25M 256MDRAM will have to Thin to 8nm. For high-performance CMOS logic circuit, the requirements of the film in the film than an earlier era, for the 0.25μm process, it requires the use of 6nm such a very thin oxide film. In order to reduce the impact of hot carriers on the reliability, the power supply voltage will be lowered from 5V some, all kinds of gate oxide film will be attached to a certain electric field. However, for high integration, due to the chip area increases, that is, with the gate area increases and if