提出了一种适用于分数分频锁相环频率综合器的全数字噪声整型ΔΣ调制器电路结构新的设计方法,并将其最终实现.采用了流水线技术和新的CST算法优化多位输入加法器结构,从而降低了整体的复杂度和功耗.这种电路结构通过了Matlab的行为级仿真,ASIC全定制实现并流片,该结构也通过VHDL综合实现验证,最后给出的测试结果表明该电路具有良好的性能,可应用于单片千兆赫兹级低功耗CMOS频率综合器中. A new design method of full digital noise integral ΔΣ modulator circuit architecture for Fractional-N PLL frequency synthesizer is proposed and finally implemented.The pipeline technology and the new CST algorithm are used to optimize the multi-bit input Adder structure, thus reducing the overall complexity and power consumption.This circuit structure through the Matlab simulation of the behavioral level, ASIC-based custom realization and flow sheet, the structure is also verified by the VHDL synthesis, and finally gives the test results Indicating that the circuit has good performance, can be applied to a single gigahertz level low-power CMOS frequency synthesizer.