在IEEE国际电子器件会议(IEDM)上,IMEC报告了一项重大进展,即在32nm节点上,利用铪基高k介质和TaC金属栅极可显著提高平面CMOS的性能。通过在栅介质和金属栅之间增加一薄层介质盖可获得较低的阈值电压(Vt)和导带及价带间的有效功函数(WF)。此外,栅叠层的激光退火过程明显降低了最小的可能栅长,增 At the IEEE International Electron Devices Conference (IEDM), IMEC reported a major advance in significantly increasing the performance of planar CMOS with hafnium based high-k dielectrics and TaC metal gates on 32nm nodes. The lower threshold voltage (Vt) and the effective work function (WF) between the conduction band and the valence band are obtained by adding a thin dielectric cover between the gate dielectric and the metal gate. In addition, the laser annealing process of the gate stack significantly reduces the minimum possible gate length and gain