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Si材料中较低的空穴迁移率限制了Si互补金属氧化物半导体器件在高频领域的应用.针对SiGe p型金属氧化物半导体场效应管(PMOSFET)结构,通过求解纵向一维泊松方程,得到了器件的纵向电势分布,并在此基础上建立了器件的阈值电压模型,讨论了Ge组分、缓冲层厚度、Si帽层厚度和衬底掺杂对阈值电压的影响.由于SiGe沟道层较薄,计算中考虑了该层价带势阱中的量子化效应.当栅电压绝对值过大时,由于能带弯曲和能级分裂造成SiGe沟道层中的空穴会越过势垒到达Si/SiO2界面,从而引起器件性能的退化.建立了量子阱SiGe PMOSFET沟道层的空穴面密度模型,提出了最大工作栅电压的概念,对由栅电压引起的沟道饱和进行了计算和分析.研究结果表明,器件的阈值电压和最大工作栅压与SiGe层Ge组分关系密切,Ge组分的适当提高可以使器件工作栅电压范围有效增大.
The lower hole mobility in Si material limits the application of Si CMOS devices in high frequency applications.For SiGe PMOSFETs, by solving the one-dimensional Poisson equation in the longitudinal direction , The vertical potential distribution of the device was obtained and the threshold voltage model of the device was established.The effects of Ge composition, buffer layer thickness, Si cap layer thickness and substrate doping on the threshold voltage were discussed.Because SiGe trench When the gate voltage is too large, the holes in the SiGe channel layer will cross the potential due to band bending and energy level splitting Barrier to reach the Si / SiO2 interface, which leads to the degradation of the device performance.A model of the hole density of the channel layer of the quantum well SiGe PMOSFET is established and the concept of the maximum working gate voltage is proposed, and the channel saturation caused by the gate voltage The results show that the threshold voltage and the maximum working gate voltage of the device are closely related to the Ge composition of the SiGe layer. Appropriate increase of the Ge content can effectively increase the gate voltage range of the device.