Two layout and process key parameters for improving high voltage nLEDMOS(n-type lateral extended drain MOS) transistor hot carrier performance have been identified.Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations,for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface.This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results. Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified .creasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si / SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.