一、概要本锁相环是为某超短波接力机数据终端实现位(比特)同步而研制的.电路的特点是采用了微功耗互补场效应数字集成电路-CMOS器件作鉴相器和压控振荡器。用CMOS器件“3412”与非门组成摸二逻辑作鉴相器,具有线路简单,线性范围宽,对噪声脉冲干扰不敏感等优点。由CMOS器件“8F”反相门组 I. Summary The PLL is developed for bit (bit) synchronization of an ultrashort wave relay data terminal.The circuit is characterized by a micro-power complementary field effect digital integrated circuit -CMOS device for the phase detector and voltage control Oscillator. With the CMOS device “3412” NAND gate composed of touch two logic for the phase detector, with a simple line, a wide linear range, noise pulse interference is not sensitive to other advantages. By the CMOS device “8F” anti-phase gate group