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一、引言在C—V测试法广泛应用于工艺监控和理论研究的当今,如何全面了解C—V特性的不稳定因素并加以有效控制,从而掌握最佳测试条件是十分必要和急待解决的课题。特别对CCD和n沟MOS有源器件制造过程的工艺监控,将遇到大量低掺杂P型硅MOS结构的C—V测试问题,C—V不稳定因素极为复杂。文献[1]研究了正电荷侧向铺伸效应造成的C—V不稳定性;文献[2]提出了消除方法。文献[3-6]曾利用雪崩和隧道效应机构讨论了这个问题,指出强电场下雪崩效应是主要因素。我们在实验中观察到,当采取适当措施避开文献[1]和
I. INTRODUCTION Nowadays, C-V test method is widely used in process monitoring and theoretical research. Nowadays, it is very necessary and urgent to grasp the instability factors of C-V characteristic and to effectively control it. Question. In particular, the process monitoring of manufacturing processes for CCD and n-channel MOS active devices will encounter C-V test problems with a large number of low-doped P-type silicon MOS structures, and the C-V instability is extremely complicated. Reference [1] studied the C-V instability caused by the lateral spread effect of positive charge. The elimination method was proposed in [2]. The literature [3-6] discussed this issue with avalanches and tunneling mechanisms, pointing out that the avalanche effect is a major factor under strong electric fields. We observed in the experiment when taking appropriate measures to avoid the literature [1] and