This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication.The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer(FFE) and a two-tap half-rate decision feedback equalizer(DFE) in order to cancel both pre-cursor and post-cursor ISI.By employing an active-inductive peaking circuit for the delay line,the bandwidth of the FFE is increased and the area cost is minimized.CML-based circuits such as DFFs,summers and multiplexes all help to improve the speed of DFEs.Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V.The overall chip area including pads is 0.3 0.5 mm2. This paper presents a 0.18 μm CMOS 6.25 Gb / s equalizer for high speed backplane communication. The proposed equalizer is a combined one-of-one feed tap-forward equalizer (FFE) and a two-tap half- DFE) in order to cancel both pre-cursor and post-cursor ISI.By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs , summers and multiplexes all help to improve the speed of DFEs.Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb / s data passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V.The overall chip area includes pads of 0.3 0.5 mm2.