Equipped with 512-bit wide SIMD instructions and large numbers of computing cores,the emerging x86-based Intel Many Integrated Core(MIC) Architecture provides not only high floating-point performance,but also substantial off-chip memory bandwidth. The 3D FFT(three-dimensional fast Fourier transform) is a widely-studied algorithm; however,the conventional algorithm needs to traverse the data array three times. In each pass,it computes multiple 1D FFTs along one of three dimensions,giving rise to plenty of non-unit strided memory accesses. In this paper,we propose a two-pass 3D FFT algorithm,which mainly aims to reduce the amount of explicit data transfer between the memory and the on-chip cache.The main idea is to split one dimension into two sub-dimensions,and then combine the transform along each sub-dimension with one of the rest dimensions respectively. The difference in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. Multi-level parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of local cache. On top of this,a number of optimization techniques,such as memory padding,loop transformation and vectorization,are employed in our implementation to further enhance the performance.We evaluate the algorithm on the Intel Xeon PhiTMcoprocessor 7110 P,and achieve a maximum performance of 136 Gflops with 240 threads in offload mode,which beats the vendor-specific Intel MKL library by a factor of up to 2.22 X. Equipped with 512-bit wide SIMD instructions and large numbers of computing cores, the emerging x86-based Intel ™ Many Integrated Core (MIC) Architecture provides not only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT Three-dimensional fast Fourier transform is an widely-studied algorithm; however, the conventional algorithm needs to traverse the data array three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of non -unit strided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce the amount of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into The difference in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. Multi-leve l parallelism is leverage on the many-core system for a high degree of parallelism and better data reuse of local cache. On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectorization, are employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel Xeon PhiTM processor 7110 P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which beats the vendor-specific Intel MKL library by a factor of up to 2.22 X.