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随着电子设备制造厂商推出体积更小、传输速度更快的产品，多芯片封装技术越来越受到关注。通过把相互连接的几个芯片封装在一个管壳里，其基板尺寸可减小到１／１０或更小，且芯片之间的信号传输速度提高２倍。即使如此，多芯片组件也仅仅使用在那些能以最经济的方法获得理想结果的地方。本文将讨论用于设计、制造和测试一个低成本高密度多芯片组件所需要的一套方法和基板结构，该组件可容纳六个高速ＡＳＩＣ逻辑器件。
With the introduction of electronic equipment manufacturers, smaller and faster transfer products, multi-chip packaging technology more and more attention. By encapsulating several interconnected chips in a single package, the substrate size can be reduced to 1/10 or less and the signal transfer speed between chips can be doubled. Even so, multi-chip components are only used where those are the most economical ways to achieve the desired results. This article discusses a set of methods and substrate structures needed to design, manufacture, and test a low-cost, high-density multi-chip package that accommodates up to six high-speed ASIC logic devices.