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介绍了一种用于高速流水线ADC双沿采样的时钟占空比稳定电路。在传统占空比稳定电路的基础上,增加含连续时间积分器的反馈环路,并设计了时钟周期检测电路,同时可通过SPI配置积分器的参考电压,在片外调节芯片制造过程中产生的误差,并在前端增设一个高增益带宽时钟放大器,用来放大幅度很小(Vp-p<100mV)的差分输入时钟信号。电路采用0.18μm 1.8V 1P5MCMOS工艺,可对频率范围为50~250MHz、占空比范围为10%~90%的输入时钟进行稳定调节,时钟峰-峰值抖动约为0.3ps@250MHz。
A clock duty cycle stabilization circuit for double-edge sampling of high-speed pipeline ADCs is presented. Based on the traditional duty cycle stabilization circuit, a feedback loop with a continuous-time integrator is added and a clock cycle detection circuit is designed. At the same time, the reference voltage of the integrator can be configured through the SPI to generate the off-chip regulation chip during manufacturing Error amplifier. A high-gain-bandwidth clock amplifier is added to the front end to amplify the differential input clock signal with a small amplitude (Vp-p <100mV). The circuit uses a 0.18μm 1.8V 1P5MCMOS process for stable regulation of the input clock in the frequency range of 50 to 250MHz and duty cycle in the range of 10% to 90%. The clock peak-to-peak jitter is approximately 0.3ps @ 250MHz.