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在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOIMOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介电常数的增加而增大,随应变Si层的掺杂浓度的提高而增大.研究了该结构的短沟道效应SCE(short channel effect)和漏致势垒降低DIBL(drain induced barrier lowering)效应,结果表明该结构能够很好地抑制SCE和DIBL效应.
Based on the advantages of strained Si, high-k gate and SOI structure, a new type of high-k gate dielectric strained Si fully depleted SOIMOSFET structure is proposed.By solving the two-dimensional Poisson equation, the new structure A two-dimensional threshold voltage model in which the main parameters that affect the threshold voltage are taken into account and the relationship between the threshold voltage and the thickness of the Ge layer and the strained Si layer in the relaxation layer is analyzed.The results show that the threshold voltage varies with the relaxation time in the relaxation layer And the relationship between the threshold voltage and the dielectric constant of the high-k gate dielectric and the doping concentration of the strained Si layer is also analyzed.The results show that the threshold voltage increases with the increase of the high-k The dielectric constant of the dielectric increases with the increase of the doping concentration of the strained Si layer. The short channel effect (SCE) and drain induced barrier lowering effect, the results show that the structure can well inhibit the SCE and DIBL effects.