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设计人员和设计管理人员总是有很多有关面对挑战的热门话题。针对用来开发网络芯片的工具和方法学，设计人员讨论了哪些是可取的，哪些是不可取的，并介绍了他们的选择：ＡＳＩＣ对ＦＰＧＡ；ＨＤＬ对Ｃ或其他高级语言；用户自有的工具对ＡＳＩＣ厂商模型；最佳分类工具（Ｂｅｓｔ－ｉｎ－ｃｌａｓｓ ｔｏｏｌｓ）对集成成套工具。
Designers and design managers have always had a lot of talk about the challenges. For tools and methodologies used to develop networking chips, designers discussed what is desirable and what is not, and describes their options: ASIC vs. FPGA; HDL vs. C or other high-level languages; and user-owned Tool to ASIC vendor model; Best-in-class tools to integration kits.