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A novel silicon controlled rectifier(SCR) with high holding voltage(Vh) for electrostatic discharge(ESD) protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N+ layer(LN+) and a long P+ layer(LP+), which divide the conventional low voltage trigger silicon controlled rectifier(LVTSCR) into two SCRs(SCR1: P+/Nwell/Pwell/N+ and SCR2: P+/LN+/LP+/N+) with a shared emitter. Under the low ESD current(IESD), the two SCRs are turned on at the same time to induce the first snapback with high V_h(V_(h1)). As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h(V_(h2)). The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like(Transmission Line Pulse-like) simulation. An optimized V_(h2) of 7.4 V with a maximum failure current(I_(t2)) of 14.7 m A/μm is obtained by the simulation.
A novel silicon controlled rectifier (SCR) with high holding voltage (Vh) for electrostatic discharge (ESD) protection is proposed and investigated in this paper. The proposed SCR critical high Vhby adding a long N + layer (LN +) and a long P + LP +), which divides the conventional low voltage trigger silicon controlled rectifier (LVTSCR) into two SCRs (SCR1: P + / Nwell / Pwell / N + and SCR2: P + / LN + / LP + / N + (IESD), the two SCRs are turned on at the same time to induce the first snapback with high V_h (V_h1). As the IESDincreases, the SCR2 will be turned off because of its low current gain. Thus, the IESDwill The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like (Transmission Line) flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h (V_h2) An optimized V_ (h2) of 7.4 V with a maximum failure current (I_ (t2)) of 14.7 m A / μm is obtained by the simulation.