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占空比(Duty Cycle)在电信领域中有如下含义:在一串理想的脉冲序列中(如方波),正脉冲的持续时间与脉冲总周期的比值。例如:脉冲宽度1μs,信号周期4μs的脉冲序列占空比为0.25。在一段连续工作时间内脉冲占用的时间与总时间的比值。在CVSD调制(continuously vatiable slope delta modulation)中,比特“1”的平均比例(未完成)。在周期型的现象中,
Duty cycle has the following meaning in the field of telecommunications: The ratio of the duration of a positive pulse to the total period of a pulse in a perfect series of pulses (such as a square wave). For example: the pulse width 1μs, the signal cycle 4μs pulse sequence duty cycle of 0.25. The ratio of the time the pulse takes to the total time over a period of continuous working time. In CVSD modulation (continuously vatiable slope delta modulation), the average ratio of bits “1 ” (unfinished). In the periodic phenomenon,