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基于CSMC 0.5μm FEOL/0.35μm BEOL Mixed Signal工艺,利用gm/ID设计方法,即以工艺库中BSIM3V3模型数据绘制出的gm/ID~Vgs关系曲线为基本出发点,结合其他参数及指标实现了折叠式共源共栅结构两级CMOS运算放大器的电路参数及版图设计。Hspice仿真结果表明,电路在3.3V工作电压下,低频开环电压增益为87.4d B,相位裕度为76°,单位增益带宽积为4.92MHz。利用gm/ID方法设计运算放大器,在保证电路性能的基础上具有设计流程简单、工艺一致性及设计可移植性好等优点。
Based on the CSMC 0.5μm FEOL / 0.35μm BEOL Mixed Signal process, the gm / ID design method, that is, the gm / ID ~ Vgs curve drawn from the BSIM3V3 model data in the process library is taken as the starting point, and the folding is achieved by combining other parameters and indexes Circuit Parameters and Layout Design of Two Cascaded CMOS Operational Amplifiers with. Hspice simulation results show that the circuit under the 3.3V operating voltage, low-frequency open-loop voltage gain of 87.4d B, the phase margin of 76 °, unity gain bandwidth product is 4.92MHz. The use of gm / ID design op amp, to ensure that the circuit performance based on a simple design process, process consistency and design portability and so on.