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在单晶硅衬底上,通过三次外延和两次选择性掺杂,实现了一种新型的半绝缘结构。其中有一个隔离岛和衬底之间是非绝缘的,将纵向器件制作在此隔离岛中将不需要额外的体引出结构。相邻的隔离岛之间可通过反向偏置的pn结进行隔离,也可由填充二氧化硅和非掺杂多晶硅形成的介质隔离槽实现隔离。在外延层中进行多次选择性地掺杂反型杂质,经高温退火后形成夹层,将此夹层引出到硅片表面后偏置在合适的电位即可实现顶层和底层之间的隔离。电参数测试得到外延层和夹层之间形成的pn结的耐压为179 V,介质隔离槽的耐压为138 V。SEM图像显示介质隔离槽得到很好地实现。
On the single crystal silicon substrate, a new type of semi-insulating structure is realized by three times of epitaxy and twice selective doping. One of the isolation islands and the substrate are uninsulated, and the fabrication of the vertical device in this isolation island will not require additional body extraction structures. Adjacent isolation islands can be isolated by reverse-biased pn junctions, or by dielectric isolation trenches formed of filled silicon dioxide and non-doped polysilicon. In the epitaxial layer to carry out multiple selective inversion of impurities, the high temperature annealing after the formation of the sandwich, the sandwich layer leads to the surface after the bias at the appropriate potential to achieve isolation between the top and bottom. The electrical resistance of the pn junction formed between the epitaxial layer and the interlayer was 179 V and the withstand voltage of the dielectric isolation trench was 138 V. The SEM image shows that the media isolation groove is well realized.