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一、引言 二维阵列结构是一种用途广泛的易于在VLSI中实现的结构。由于这种结构适合于开发并行运算,所以矩阵相乘、傅里叶变换、卷积等信号处理运算均可采用二维阵列结构。但这 种结构的弱点是,一旦阵列中的某一个单元出现故障,它将影响整个阵列的正常运行。为了提高二维阵列的可靠性,在这种结构中引入容错是必要的。 对于二维阵列的容错设计,目前有两类方法:一是结构冗余法,即提供冗余硬件;二是时间冗余法,即通过加倍处理时间实现容错。
I. Introduction Two-dimensional array structure is a versatile and easy-to-implement structure in VLSI. Because of this structure is suitable for the development of parallel computing, so matrix multiplication, Fourier transform, convolution and other signal processing operations can use two-dimensional array structure. However, the weakness of this architecture is that once a cell in the array fails, it will affect the normal operation of the entire array. In order to improve the reliability of the two-dimensional array, it is necessary to introduce fault tolerance into such a structure. There are two kinds of methods for fault-tolerant design of two-dimensional array: one is the structural redundancy method, which provides redundant hardware; the other is the temporal redundancy method, which is to achieve fault tolerance by doubling the processing time.