传统分数倍采样率变换方案应用于宽带全数字接收机系统时,部分数字电路处理速率将高达GHz量级,这成为系统数字实现的瓶颈。该文从分数倍采样基本原理出发,通过对升采样与多相滤波器级联响应进行推导分析,得出一种改进的分数倍采样率变换方案,使得高时钟数字电路得以避免。改进方案与传统方案的电路综合结果对比证明了理论分析的正确性。结果表明,改进方案对数字器件处理速率的需求仅为传统方案的1/min{I,D},且不受采样率变换比例I/D的影响,I与D分别为内插倍数与抽取倍数。 When the traditional fractional-sampling rate conversion scheme is applied to a wideband all-digital receiver system, part of the digital circuit processing rate will reach the order of GHz, which becomes the bottleneck of digital system implementation. In this paper, starting from the basic principle of fractional-time sampling, an improved fractional-fold sampling rate conversion scheme is derived by deducing and analyzing the cascaded response of the upsampling and polyphase filter so that the high clock digital circuit can be avoided. The comparison between the improved scheme and the traditional scheme shows that the theoretical analysis is correct. The results show that the demand for digital processing rate is only 1 / min {I, D}, and is not affected by the sampling rate conversion ratio I / D. I and D are the interpolation multiples and the extraction multiples, respectively .