介绍了基于现场可编程门阵列（ＦＰＧＡ）查阅表的逻辑优化准则．基于这一准则，讨论了几种重要的逻辑优化运算，例如抽取、分解、约数检查和简化，以按照目标工艺技术估算电路的价格．基于ＦＰＧＡ，利用我们的方法对查阅表进行逻辑优化，可以得到工艺映射中的良好出发点．以２５个基准试验例子为基础，我们的优化电路所需要的构造逻辑方块（ＣＬＢ）比利用ＭＩＳ－ＩＩ的优化电路的情形下少百分之十四，如果两者都利用ＭＩＳ－ｐｇａ顺序映射的话．此外，电路的级数也稍有改进． The logic optimization guidelines based on Field Programmable Gate Array (FPGA) look-up tables are introduced. Based on this guideline, several important logic-optimization operations are discussed, such as decimation, decomposition, divisor checks, and simplifications to estimate the price of the circuit according to the target process technique. Based on the FPGA, using our method to logically optimize the look-up table, you get a good starting point in the process map. Based on 25 benchmark test cases, our optimization circuit requires a minimum of 14% fewer building blocks (CLBs) than in the case of MIS-II optimized circuits, and if both utilize the MIS-pga sequential mapping if. In addition, the circuit series also slightly improved.