论文部分内容阅读
以电阻电容充放电正反馈网络为基础,设计了具有固定振荡频率的RC振荡电路,设计中考虑了电源电压和温度变化对振荡频率的影响,进行了优化设计,同时利用低压差稳压器(LDO)消除MOS管的沟道调制效应。该振荡电路可作为数字逻辑控制电路的时钟信号,推动电路逻辑的进行,并为延时信号提供时间基准。电路基于华润上华公司(CSMC)0.35μm n阱双层多晶硅和三层金属(DPTM)工艺设计仿真,后仿真和测试结果表明利用该技术设计的RC振荡电路分频后可产生具有较高的精度的37.5 kHz信号,可作为数字逻辑部件的时钟信号源,满足设计要求。
Based on the positive feedback network of the resistor-capacitor charging and discharging, an RC oscillator circuit with a fixed oscillation frequency is designed. The influence of the power supply voltage and temperature on the oscillation frequency is taken into consideration in the design, and the optimal design is made. At the same time, the low dropout voltage regulator LDO) to eliminate the MOS channel modulation effect. The oscillator circuit can be used as a digital logic control circuit clock signal to promote the logic of the circuit, and to provide time-delayed signal basis. The circuit is based on CSMC 0.35μm n-well double-layer polysilicon and triple-layer metal (DPTM) process design simulation. The simulation and test results show that the RC oscillator circuit designed by this technology can produce high-frequency The precision 37.5 kHz signal can be used as the clock source for digital logic components to meet design requirements.