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A synchronous buck DC-DC converter with an adaptive multi-mode controller is proposed.In order to achieve high efficiency over its entire load range,pulse-width modulation(PWM),pulse-skip modulation(PSM) and pulse-frequency modulation(PFM) modes were integrated in the proposed DC-DC converter.With a highly accurate current sensor and a dynamic mode controller on chip,the converter can dynamically change among PWM, PSM and PFM control according to the load requirements.In addition,to avoid power device damage caused by inrush current at the start up state,a soft-start circuit is presented to suppress the inrush current.Furthermore,an adaptive slope compensation(SC) technique is proposed to stabilize the current programmed PWM controller for duty cycle passes over 50%,and improve the degraded load capability due to traditional slope compensation.The buck converter chip was simulated and manufactured under a 0.35μm standard CMOS process.Experimental results show that the chip can achieve 79%to 91%efficiency over the load range of 0.1 to 1000 mA.
A synchronous buck DC-DC converter with an adaptive multi-mode controller is proposed.In order to achieve high efficiency over its entire load range, pulse-width modulation (PWM), pulse-skip modulation (PSM) and pulse-frequency modulation PFM) modes were integrated in the proposed DC-DC converter.With a highly accurate current sensor and a dynamic mode controller on chip, the converter can dynamically change among PWM, PSM and PFM control according to the load requirements.In addition, to avoid power device damage caused by inrush current at the start up state, a soft-start circuit is presented to suppress the inrush current. Futurertherm, an adaptive slope compensation (SC) technique is proposed to stabilize the current programmed PWM controller for duty cycle passes over 50%, and improve the degraded load capability due to traditional slope compensation. The buck converter chip was simulated and manufactured under a 0.35 μm standard CMOS process. Experimental results show that the chip can achieve 79% to 91% efficiency over the load range of 0.1 to 1000 mA.