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提出了一种任意阶基于最小均方误差(LMS)自适应时延估计(LMSTDE)算法的现场可编程逻辑门阵列(FPGA)结构化设计方法.将原有的低阶次LMSTDE算法中速度受限的顺序迭代运算优化为只包含误差更新和权系数更新操作的全并行乘/加运算,并进一步分离为不依赖于阶次变量的功能运算单元,最后将软件设计中的结构化方法运用到FPGA的硬件设计中,实现了FPGA资源约束内的任意阶次全并行LMSTDE算法.仿真与性能验证表明:采用结构化设计方法实现的全并行LMSTDE算法提高了时延运算速度,在阶次上易于伸缩,并未改变原算法的误差收敛特性.
An FPGA-based structural design method based on Least Mean Square Error (LMS) Adaptive Time Delay Estimation (LMSTDE) algorithm is proposed in this paper. The original low order LMSTDE algorithm The sequential iterative operation is optimized to include full parallel multiply / add operation of error update and weight coefficient update operation and further separated into functional operation units that do not depend on order variables. Finally, the structured method in software design is applied to The hardware design of FPGA realizes all-order LMSTDE algorithm with arbitrary FPGA resource constraints.The simulation and performance verification show that the full parallel LMSTDE algorithm using structured design method can improve the delay operation speed and is easy to be orderly Scaling does not change the original algorithm error convergence characteristics.