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针对传统固定交织器灵活性和适应性差的特点,在LTE标准下,提出了一种基于FPGA的可变帧长QPP交织器的硬件实现方案。采用“自上而下”的设计思想和“自下而上”的实现流程相结合的方法,根据FPGA自身特点,将QPP交织算法巧妙地转化为硬件语言进行描述,对特定功能模块进行优化设计后调试统一。将设计的交织器应用于Turbo码编译码器中,下载配置到Xilinx公司的Virtex-2 Pro系列芯片,依据信道环境修改编码码长,使译码性能与时延达到最佳平衡,具有很好的移植性和通用性。
Aiming at the characteristics of poor flexibility and adaptability of traditional fixed interleaver, a hardware implementation scheme of variable frame length QPP interleaver based on FPGA is proposed under the LTE standard. According to the characteristics of FPGA, the QPP interleaving algorithm is subtly transformed into the hardware language to describe the method of combining the design idea of “top-down” with the implementation process of “bottom-up” After the optimization of the module design debugging unified. The designed interleaver is applied to the Turbo codec, and the Virtex-2 Pro series chip configured to Xilinx is downloaded to modify the code length according to the channel environment to achieve the best balance of decoding performance and delay, which is very good The portability and versatility.