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设计实现了一种基于CORDIC算法和乘法器的直接数字频率合成器。采用混合旋转算法实现相位幅度转换,最高工作频率达到400MHz。在算法级,将DDFS中需要执行的π/4旋转操作分成两次旋转完成,第一次旋转采用CORDIC算法,第二次旋转采用乘法器来完成,同时采用流水线结构来实现累加器,提高整体性能。在晶体管级,采用DPL(Double-pass-transistor logic)逻辑实现基本电路单元,减少延迟提高速度。经0.35μmCMOS工艺流片,在400MHz的工作频率下,输出信号在80MHz处,SFDR为76.47dB,整个芯片面积为3.4mm×3.8mm。
Design and implementation of a direct digital frequency synthesizer based on CORDIC algorithm and multiplier. Hybrid rotation algorithm to achieve the phase amplitude conversion, the maximum operating frequency of 400MHz. At the algorithm level, the π / 4 rotation needed to be performed in DDFS is divided into two rotations, the first rotation is CORDIC algorithm, the second rotation is performed by multiplier, and the pipeline structure is used to implement the accumulator to improve the whole performance. At the transistor level, DPL (Double-pass-transistor logic) logic is used to implement the basic circuit unit, reducing the delay increase speed. The 0.35μm CMOS process chip, at 400MHz operating frequency, the output signal at 80MHz, SFDR 76.47dB, the entire chip area of 3.4mm × 3.8mm.