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提出了两种新的电路技术,在降低多输入多米诺“或门”的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺“或门”并基于45nm BSI M4 SPICE模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8·8 %和11·8 %,电路速度分别提高了9·5 %和13·7 %,同时总的漏电流分别降低了80·8 %和82·4 %.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.
Two new circuit technologies are proposed, which can reduce the leakage current and improve the noise margin of the circuit while reducing the dynamic power consumption of the multi-input domino orbit.A new eight-input domino “ Or gate ”based on the 45nm BSI M4 SPICE model.The simulation results show that the two new domino circuits are designed to effectively reduce the dynamic power consumption and reduce the total leakage current under the same noise margin, Compared with the double-threshold domino circuit, the dynamic power consumption of the two circuits is reduced by 8.8% and 11.8% respectively, and the circuit speed is increased by 9.5% and 13.7% respectively. At the same time, the total leakage current is decreased by 80.8% and 82.4% respectively. Based on the simulation results, the influence of different logic states on the total leakage current of the double-threshold domino circuit is also analyzed.