本专利介绍一种双层多晶硅硅栅存储器。它有一个用来存储电荷的浮置栅和一个控制栅。该存储器件可做存储阵列中的单单元,采用双自对准方法,在进行栅掺杂的同时形成源漏区。在以控制栅为基硅形成主源漏区之前,先安排一前予淀积,以浮置栅力基准进行轻掺杂,形成次源漏区。 This patent describes a double-layer polysilicon silicon gate memory. It has a floating gate and a control gate for storing charges. The memory device can be used as a single cell in a memory array. A dual self-alignment method is used to form the source and drain regions while performing gate doping. Before controlling the gate as a base silicon to form the main source drain region, a first pre-deposition is arranged and lightly doped with a floating gate reference to form a secondary source drain region.