Verilog HDL语言是一种应用广泛的标准硬件设计语言。利用硬件设计语言进行数字系统设计也已成为一种趋势。文中着重讨论了利用 Verilog HDL语言设计 Viterbi译码器的过程 ,并就各种设计中出现的问题进行了分析。最后给出了实现结果 Verilog HDL language is a widely used standard hardware design language. The design of digital systems using hardware design language has also become a trend. This paper focuses on the design of Viterbi decoder using Verilog HDL language and analyzes the problems in various designs. Finally, the achievement is given