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设计了一种适合于无线传感网(WSN)结点SoC芯片传感器接口电路应用的12 bit精度逐次逼近型(SAR)模数转换器(ADC)。为了实现高精度、低成本,并兼容射频CMOS工艺的要求,利用全差分结构和带有Auto-zero失调消除功能的比较器提高转换精度。采用分段式电容阵列DAC减小芯片占用面积,通过构造符合精度要求的MOM电容单元,使电容阵列符合射频CMOS的工艺特点,利于嵌入式应用。同时,采取增加辅助电容的办法扩大输入信号范围。该ADC在0.18μm 1P6M标准CMOS工艺下实现,版图面积为0.9 mm2,最高采样速率为1 MS/s,在1.8 V电源电压下,整体功耗仅为2 mW。
A 12-bit precision successive approximation (SAR) analog-to-digital converter (ADC) suitable for WSN node SoC chip sensor interface circuit is designed. To achieve high accuracy, low cost, and compatibility with RF CMOS processes, a fully differential architecture and comparator with Auto-zero offset cancellation are used to improve conversion accuracy. The use of segmented capacitor array DAC to reduce the chip footprint, through the construction of MOM capacitor units meet the accuracy requirements, the capacitor array in line with RF CMOS process features conducive to embedded applications. At the same time, to increase the auxiliary capacitor approach to expand the input signal range. The ADC is implemented in a 0.18μm 1P6M standard CMOS process with a footprint of 0.9 mm2 and a maximum sampling rate of 1 MS / s with an overall power consumption of only 2 mW at 1.8 V supply.