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介绍了一种由两个交叉耦合反向器构成的6-晶体管(6-T)存储单元的噪声容限分析方法。对6-T CMOS SRAM单元的稳定性作了分析及仿真。借助SPICE和MATLAB工具,对存储单元在数据保持和数据读取时的稳定性、数据写入过程中的可靠性及其之间的关系进行了深入研究。对可能影响噪声容限的因素,如单元比、上拉比、MOS管的阈值电压、位线预充电压、电源电压以及温度进行了仿真讨论,并从中得到合适的电路设计参数。流片结果表明,理论分析与实测数据相符。分析数据对基于CSMC 0.5μm CMOS工艺的SRAM电路设计优化具有指导作用。
A noise margin analysis method for a 6-transistor (6-T) memory cell consisting of two cross-coupled inverters is presented. The stability of the 6-T CMOS SRAM cell was analyzed and simulated. With the help of SPICE and MATLAB tools, the stability of the memory cell during data retention and data read, the reliability of data writing and the relationship between them are deeply studied. Factors that may affect the noise margin, such as the cell ratio, the pull-up ratio, the threshold voltage of the MOS transistor, the bit line precharge voltage, the power supply voltage and the temperature are simulated and discussed, and the appropriate circuit design parameters are obtained. Flowsheet results show that the theoretical analysis and measured data line. Analyzing data is instructive in the design and optimization of SRAM circuits based on the CSMC 0.5μm CMOS process.