一、引言 硅外延工艺曾对器件工艺产生了变革性的影响。近年来,随着器件的发展,对硅外延材料提出了更高的要求。在采用低位错单晶和汽相原位腐蚀工艺后,硅外延材料的位错已能稳定地控制在100/cm~2以下,层错控制在<10/cm~2以下。但是众所周知,有些外延片虽然电阻率、厚度、层错、位错数值基本相同,制管结 I. INTRODUCTION The silicon epitaxial process has had a transformative effect on the device technology. In recent years, with the development of the device, the silicon epitaxial material is put forward higher requirements. After using low dislocation single crystal and vapor phase in-situ etching process, the dislocations of the silicon epitaxial material can be stably controlled below 100 / cm 2 and the stacking fault is controlled below 10 / cm 2. However, as we all know, although some epitaxial wafers resistivity, thickness, stacking fault, dislocation values ​​are basically the same, pipe knot