A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range. A 320 × 240 CMOS image sensor is demonstrated, which is implemented by a standard 0.6 μm 2P2M CMOS process. For reducing the chip area, each 2 × 2-pixel block shares a sample / hold circuit, analog-to-digital converter and 1 -b memory.The 2 × 2 pixel pitch has an area of ​​40 μm × 40 μm and the fill factor is about 16% .While operating at a low frame rate, the sensor dissipates a very low power by power-management circuit making pixel -level comparators in an idle state. A digital correlated double sampling, which eliminates fixed pattern noise, improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.