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为实现大规模集成,必须提高管芯成品率。我们在不掺金的I~2L 工艺中,在单晶片和外延片流程上做大β值的管芯,长期都没有达得理想的成品率。因此,如何稳定基本工艺,提高管芯成品率,真正实现复杂逻辑功能在单片上集成,这是我们的重要任务。本文提出氧化前硬Si_3N_4背面萃取(吸收)工艺,能有效地提高管芯成品率。一、问题的提出多年来,我们在I~2L 工艺流程中,经常发现硼扩散(X_(?)b≤1.5μ)后,测量单结反向击穿特性是好的;但磷扩散后,三极管特性不好。通常看到有“二次”、“扫把”、“杵
To achieve large-scale integration, die yield must be increased. We do not gold in the I ~ 2L process, in the process of single-chip and epitaxial wafer β value of the core, the long-term have not reached the desired yield. Therefore, how to stabilize the basic process, improve die yield, and truly realize the integration of complex logic functions on a single chip is an important task for us. In this paper, the back extraction (absorption) process of hard Si_3N_4 before oxidation is proposed, which can effectively improve the yield of die. First, the problem raised Over the years, we in the I ~ 2L process, we often found that boron diffusion (X _ (?) B≤1.5μ), the measured single junction reverse breakdown is good; Transistor characteristics are not good. Usually see the “second”, “broom”, "pestle